Pmos
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PMOS transistor operation characteristics CMOS
PMOS Transistor (P-Channel MOSFET)
A PMOS (P-channel Metal-Oxide-Semiconductor) transistor is one of the two fundamental building blocks of CMOS (Complementary MOS) digital logic - the other being NMOS.
Structure
PMOS is built on an n-type substrate with two p-type doped regions (source and drain). Between them, a thin silicon dioxide (SiO₂) gate oxide insulates the metal gate electrode from the semiconductor. It has 4 terminals: Gate (G), Source (S), Drain (D), Body (B).
How It Works
PMOS uses holes (positive charge carriers) as the majority current carrier - the dual of NMOS which uses electrons.
| Gate Voltage | State | Current Flow |
|---|---|---|
| LOW (0V / Logic 0) | ON | Yes - holes form a channel |
| HIGH (VDD / Logic 1) | OFF | No |
- The threshold voltage (Vt) is negative (typically -0.3V to -0.7V in modern processes)
- The transistor turns ON when V_GS < V_tp (i.e., gate is sufficiently below the source voltage)
- Source is typically connected to VDD (positive supply)
Operating Regions
| Region | Condition | Behavior |
|---|---|---|
| Cutoff | V_GS > V_tp | No channel, transistor OFF |
| Linear (Triode) | V_DS > V_GS - V_tp | Current flows, acts like a resistor |
| Saturation | V_DS ≤ V_GS - V_tp | Current nearly constant, used for amplification |
PMOS vs NMOS
| Property | PMOS | NMOS |
|---|---|---|
| Carriers | Holes | Electrons |
| Substrate | N-type | P-type |
| Threshold voltage (Vt) | Negative (~-0.5V) | Positive (~+0.5V) |
| Turns ON when | Gate LOW | Gate HIGH |
| Speed | Slower | Faster (~2x) |
| Mobility | ~2x lower | ~2x higher |
PMOS is slower than NMOS because hole mobility (~450 cm²/V·s) is roughly half that of electron mobility (~1400 cm²/V·s). This is why PMOS transistors are typically made wider than NMOS in CMOS circuits to balance drive strength.
Role in CMOS Logic
In a CMOS gate, PMOS and NMOS transistors are paired in a complementary arrangement:
- PMOS forms the pull-up network - connects the output to VDD when the output should be HIGH
- NMOS forms the pull-down network - connects the output to GND when the output should be LOW
This complementary design means no DC current flows in steady state (only during switching), giving CMOS its hallmark low power consumption.
Example - CMOS Inverter:
- Input HIGH → NMOS ON, PMOS OFF → Output LOW
- Input LOW → PMOS ON, NMOS OFF → Output HIGH
Symbol
In circuit diagrams, PMOS is distinguished from NMOS by a bubble (circle) at the gate terminal, indicating its inverted switching behavior.
Let me know if you want to go deeper into a specific aspect - I/V equations, circuit design, fabrication, or CMOS logic gates.
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